Recent years have seen a rapidly increasing demand for highly integrated mixed-signal integrated circuits (IC's). This demand is mostly driven by the ever-expanding communications industry. However, as the level of integration increases, more and more mixed-signal components are becoming buried deep inside large amounts of digital circuitry without any external I/O access. This creates a difficult problem for initial device and circuit characterisation and diagnosis, as well as during a production test. For example, to measure the bias current for a high precision ADC circuit requires some form of external access. However, the access mechanism, such as a test bus, can introduce additional noise from off-chip sources.
Typically circuit characterisation includes the determination of the electrical characteristics of a circuit such as for example measuring the input/output impedance of an amplifier circuit, or finding the voltage transfer characteristics of an amplifier circuit or transistor device amongst others.
One particular area of IC testing that is being affected is the DC parametric tests. These tests are typically conducted to characterise a wide variety of mixed-signal circuits such as Analog-to-Digital Converters (ADCs), PLLs and bias networks. Also, these tests are used in digital test applications such as pad current leakage and IDDQ tests. For example, the pad current leakage test and the IDDQ test are common test techniques for detecting faults in digital ICs.
DC parametric tests are generally classified as one of two types. The first type of DC parametric test involves forcing a voltage at a circuit node while measuring the current that flows into the node. Commonly used method for on-chip current measurements include using device having either a transimpedance amplifier, as shown in FIG. 1a), an integrating network as shows in FIG. 1b) or a shunt resistance, as shown in FIG. 1c). For additional information regarding the above mentioned methods, the reader is invited to refer to the following documents:                1. Teradyne, Inc., “Low Current Ammeter Channel Card”, Advanced Mixed-Signal Instrumentation Manual, 1996.        2. C. D. Thompson, S. R. Bernadas, “A Digitally-Corrected 20b Delta-Sigma Modulator”, Proc. IEEE International Solid-State Circuits Conference, pp. 194-195, 1994.        3. U.S. Pat. No. 5,274,375 issued to Charles D. Thompson Dec. 28, 1993;        4. M. Breten, T. Lehmann, E. Bruun, “Integrating Data Converters for Picoampere Currents from Electrochemical Transducers”, Proc. IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 709-712, May 2000.        5. C. B. Wang, J. Todsen, T. Kalthoff, “A Dual Channel 20 Bit Current-Input A/D Converter for Photo-Sensor Applications”, Proc. Southwest Symposium on Mixed-Signal Design, pp. 57-60, 2000.        6. Burr-Brown Product #DDC 112        7. J. Kotowski, B. McIntyre, J. Parry, “Current Sensor IC Provides 9 bit+Sign Result without External Sense Resistor”, Proc. IEEE Custom Integrated Circuits Conference, pp. 35-38, 1998;        8. U.S. Pat. No. 5,867,054 issued to Jeffrey P. Kotowski Feb. 2, 1999;        9. National Semiconductor Product # LM3814The contents of the above documents are hereby incorporated by reference.        
A deficiency of devices of the type described above is that they involves the use of elaborate Analog-to-Digital Converters (ADCs) with trimmed components, which makes these devices expensive and relatively non-scalable for on-chip implementation. Another deficiency of devices of the type described above is that they make use of op-amps (operational amplifiers) which also makes them relatively non-scalable for on-chip implementation. Generally, the size of the op-amp circuit does not shrink to the same extent as the size of logic circuits do as IC technology advances.
The second type of DC parametric test involves forcing a known current into a circuit node while measuring the voltage at the node.
A deficiency of commonly used on-chip current sources is that they generally suffer from low output resistance and shifts in current levels due to process variation. Such current sources are described in W. Sansen et al., “A CMOS Temperature-Compensated Current Reference”, IEEE Journal of Solid-State Circuits, Vol. 23, pp. 821-824, June 1988 and in H. J. Oguey et al., “CMOS Current Reference Without Resistance”, IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1132-1135, July 1997 whose contents are herein incorporated by reference. Other on-chip current source implementations, of the type described in Burr-Brown Corporation, “Dual Current Source/Current Sink”, REF200 (Datasheet), October 1993 and in U.S. Pat. No. 4,792,748 issued to David M. Thomas et al. in Dec. 20, 1998, can generally achieve good current accuracy but require laser-trimmed on-chip resistors, which is costly when multiple measurement units are required on a single chip. The contents of the above documents are hereby incorporated by reference.
In the context of the above, there is a need in the industry to provide a method and device for use in performing DC parametric tests that alleviates at least in part problems associated with the existing devices and methods.